A Design Method of Mixed Synchronous-Asynchronous Circuit

Most of the digital circuits are categorized into the synchronous circuit which uses a clock signal to alter its internal state such that a digital signal is latched by a flip-flop in the timing specified by a clock signal. Therefore, even if a digital signal suffers from ”hazard” in between two consecutive raising edges of a clock signal, a correct signal is successfully latched if the signal reaches its final value before the raising edge arrives. In addition, it is also a good point of a synchronous circuit that the behavior of a circuit is easily verified by a cycle-based verifier/simulator. However, as the device size shrinks further and the system size becomes lager, delay variation becomes larger due to the variations of device parameters during fabrication process, the change of operating environment, etc. As a result, a synchronous circuit which is controlled by a global clock fails easily in timing of latching signal. On the other hand, an asynchronous circuit doesn’t use a clock signal, but uses handshake signals between components. Hence, an asynchronous circuit can realize a highly reliable system in which delay variation never causes timing error. However, since the handshake protocol becomes a time overhead, it is hard to improve a speed performance. Also, the area overhead of an asynchronous circuit tends to be large since the arrival of a signal is recognized with the change of signal value during the handshake protocol and hence a hazard-free circuit design is mandatory.